In the fabrication of integrated circuit (IC) chips, it is frequently necessary to electrically isolate devices that are formed on the surface of the chip, especially when these components operate at different voltages. Such complete electrical isolation is necessary to integrate certain types of transistors including bipolar junction transistors and various metal-oxide-semiconductor (MOS) transistors including power DMOS transistors. Complete isolation is also needed to allow CMOS control circuitry to float to potentials well above the substrate potential during operation. Moreover, complete isolation allows the design of novel Electro-Static Discharge (ESD) protection devices.
Ability to survive an ESD event is one of the key requirements for ICs. A common method for providing such ESD protection is to include one or more ESD clamp devices that are connected across the external pins of an IC. More generally, the ESD devices are connected between the input terminals of, and thus in parallel with, the circuitry that is to be protected. These clamp devices are generally designed to break down at a voltage below that which would cause damage to the internal circuitry of the IC, thus absorbing the ESD energy and protecting the IC circuitry. The most commonly used ESD clamp devices are simple diodes, NPN bipolar transistors, and grounded-gate NMOS (GGNMOS) transistors, which are designed to operate in the bipolar snapback mode.
FIGS. 1A-1C show two prior art ESD clamp devices. GGNMOS device 100 in FIG. 1A comprises a NMOS transistor 101 with drain (D) connected to input pad 102 and source (S) connected to ground pad 103. The NMOS gate (G) is connected to source through a gate resistor 104, with a value typically in the range of 1 kohm-100 kohm, and the NMOS body (B) is connected to source through internal body resistance 105 that is optimized to allow the GGNMOS to snapback due to parasitic NPN bipolar action at a reasonably low drain voltage. NPN ESD clamp device 110 in FIG. 1B comprises an NPN transistor 111 with collector (C) connected to input pad 112 and emitter (E) connected to ground pad 113. The NPN base (B) is connected to emitter through internal base resistance 114 to allow the NPN to snapback due to BVcer at a reasonably low collector voltage.
FIG. 2 shows a cross-section schematic of prior art GGNMOS device 100 from FIG. 1A. In this conventional, non-isolated CMOS process, P-well region 201, which serves as the body of the NMOS, is formed in P-type substrate 202. Therefore the body of this prior art GGNMOS is always connected to the substrate potential (“ground”). The device also includes N+ drain region 203, N+ source regions 204A and 204B, P+ contact region 205, lightly-doped drain (LDD) regions 206, gate 207, gate oxide 208, sidewall spacers 209, field oxide 210, inter-level dielectric (ILD) 211, and metal layer 212.
FIG. 3 shows a cross-section schematic of prior art NPN ESD clamp device 110 from FIG. 1B. In this conventional, non-isolated CMOS process, P-well region 301, which serves as the base of the NPN, is formed in P-type substrate 302. Therefore the body of this prior art NPN ESD clamp is always connected to the substrate potential (“ground”). The device also includes N+collector region 303, N+ emitter regions 304A and 304B, P+ contact region 305, field oxide 310, ILD 311, and metal layer 312.
The breakdown or trigger voltage of ESD clamp devices is typically limited to less than 20V by the vertical breakdown of various junctions in a given process. ESD devices with higher trigger voltages generally rely on a lateral breakdown mechanism that is prone to current crowding, making it difficult to design large structures that effectively distribute the ESD energy. The use of series connected or “stacked” ESD clamp devices would allow the trigger voltages of a several ESD clamp devices to be added to achieve higher total trigger voltage, but this requires complete isolation of the ESD clamp devices.
Fabrication of conventional CMOS in P-type substrate material does not facilitate complete isolation of its devices since every P-type well forming the body (back-gate) of NMOS transistors is shorted to the substrate potential, typically the most negative on-chip potential. One method for achieving complete isolation is epitaxial junction-isolation, which employs an N-type epitaxial layer grown atop a P-type silicon substrate and separated into electrically isolated tubs by a deep P-type isolation diffusion—one requiring high temperature processes to implement. High temperature processing causes a redistribution of dopant atoms in the substrate and epitaxial layers, causing unwanted tradeoffs and compromises in the manufacturing of dissimilar devices fabricated using one common process. Moreover, the high-temperature diffusions and epitaxy employed in epi-JI processes are generally incompatible with the large wafer diameters and advanced low-temperature processing equipment common in submicron CMOS fabs.
What is needed is a process for integrating various IC devices with ESD protection devices that allows for the formation of stacked devices, yet eliminates the need for high temperature processing and epitaxy. Ideally, such a manufacturing process should employ “as-implanted” dopant profiles—ones where the final dopant profiles remain substantially unaltered from their original implanted profiles by any subsequent wafer processing steps. Moreover, the process should be constructed in a modular architecture where devices may be added or omitted and the corresponding process steps added or removed to the integrated flow without changing the other devices available in the process's device arsenal.